Information for Cirrus Chipset Users : Tested Configurations
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## 8. Tested Configurations

For version 3.3, the following configurations have received a certain amount of testing:

CL-GD5446 with 2MB memory on PCI bus

  Support for dot clocks > 85 MHz has been fixed. At 16bpp, it has been reported that some stippled edges of window frames may be corrupted or show the wrong colors. The option "xaa_no_pixmap_cache" eliminates the problem.

CL-GD5464 with 4MB memory on PCI bus
CL-GD7543 on PCI bus

This is a list of configurations that has received testing with one or more of the changes introduced in version XFree86 3.2A. The amount of testing is very small for some of the configurations, and the summaries may be incomplete. If you can contribute, please do so. For the latest information check the latest version of this document on www.xfree86.org.

CL-GD5426 on VL-bus

  This configuration was only tested with an early version of the XAA code.

CL-GD5434 with 2MB memory on VL-bus

  MMIO operation is supported. This configuration was only tested with an early version of the XAA code.

CL-GD5436 with 2MB memory on PCI-bus

  Works OK. Non-MMIO operation might have problems.

CL-GD5446 with 2MB memory on PCI bus

  Works OK in MMIO mode. 32bpp probably doesn't work. The support for dot clocks > 85 MHz at 8bpp may or may not work.

CL-GD5462 with 2MB memory on PCI bus
CL-GD5462 with 4MB memory on PCI bus
CL-GD5464 with 4MB memory on PCI bus

  Works OK at 8bpp, 16bpp, 24bpp and 32bpp. CL-GD5464 works OK at 16bpp, -weight 555.

CL-GD7543 on PCI bus

  Works for 8bpp, 16bpp on TFT display (TI TravelMate 5000). Although the previous version, 3.2, was reported to broken, on some configurations it worked, while others were reported not to work correctly. On 800x600 displays, the recommended dot clock is 40 MHz for TFT and 33.7 MHz for a DSTN panel, with corresponding horizontal syncs of 33.7 kHz for TFT and 38.6 kHz for DSTN. However, reports indicate that the VESA standard 40 MHz 800x600 timing may cause problems. The solution is decrease the fourth horizontal timing number or use a dot clock of 36 MHz.

Some configurations for which no up-to-date testing data is available:

CL-GD5429 on VL-bus

  BitBLT operation should be fixed in 3.2. MMIO does not work, but not tested with with 3.2 or 3.2A.

CL-GD5430 on PCI-bus

  Works OK. 24bpp was broken, but should be fixed in later versions (3.2A).

CL-GD5430, and CL-GD5436 and CL-GD5446 with 1MB memory

  It would be nice to know whether these chips needs the same treatment at 16bpp as the CL-GD5434 with 1MB memory does.

CL-GD5434 with 1MB memory on PCI bus

  8bpp, 16pp and 24bpp work OK. 16bpp no longer has "static" problems. MMIO operation is supported.

CL-GD5436 and CL-GD5446 with 1MB memory

  In particular the FIFO settings for this configuration are uncertain.

CL-GD7541
CL-GD7548

  Should be compatible with 7543, but untested. Reports indicate that it worked with 3.2, and there's no reason why it shouldn't work with 3.2A.

Information for Cirrus Chipset Users : Tested Configurations
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